Memory Wall

Los Alamos National Laboratory researchers have introduced a new computing architecture designed to support extensive parallel processing, providing revolutionary data mobility. This system can manage “sparse,” or precise, memory access, which typically slows down data retrieval. By doing so, the system enables parallelism and boosts computing performance.

The technology improves performance in ways that can support various applications, such as aerodynamics, astrophysics, deep learning, bioinformatics, drug discovery, fraud detection, materials science, and signal processing.  
High-performance systems often encounter performance degradation, programming challenges, and cost inefficiencies when running data-intensive applications. The new, Los Alamos-developed approach supports efficient global parallel data movement and optimizes data access, circumventing the “memory wall” and mitigating performance bottlenecks for certain applications.

• Cost-Effective: Built from simple, low-cost components, using well-developed manufacturing processes.
• Low Power Requirements: Significantly reduces power consumption and lowers operating costs and carbon footprint for many applications,.
• Versatile Applications: Supports work in fields that require rapid parallel data movement and sparse memory access.
• Enhanced Performance: Overcomes data bottlenecks and improves compute efficiency.
• Scalable: Scales readily for deployment on small or large machine configurations. 

LANL researchers have developed a new computing architecture that enables global parallelism at full bandwidth, even with “sparse” memory access patterns. This allows high-level programming using a structured parallel operations library and the creation of optimized custom parallel operations at lower levels for better performance.  
In applications that depend on precise (sparse) memory accesses, even cutting-edge system architectures will likely have difficulty accessing and processing data smoothly. This significantly reduces computing performance. By enhancing how processors access data, and facilitating efficient high-volume global parallel data movement, it is possible to address the performance bottleneck caused by the difference in speeds between the processor and memory access.

The approach for managing sparse memory access can also be used in systems that are not designed for extensive parallel processing. In systems like these, the advanced memory technology developed by the Laboratory can be combined with a high-end processor. This enables the system to handle multiple small data accesses simultaneously, known as “scatters” and “gathers,” using a specific memory area controlled by the application. 

• National Security: Enhances performance in critical cybersecurity, cryptography, and secure communications applications.
• Molecular Dynamics: Supports research related to molecular and biological processes and supports performance and efficiency in a vast marketplace.
• Fraud Detection: Improves computational performance for analyzing large transaction-graph datasets.
• Drug Discovery: Accelerates molecular and biological computations that are essential for pharmaceutical research.
• AI/ML Models: Optimizes training and inference operations, resulting in reduced power consumption and improved performance.
• Interferometry: Efficiently handles phased arrays that require global “transpose” and “shift” operations.
• Embedded Systems: Provides advanced parallel performance with low power consumption for small embedded systems.

To advance this technology, the Laboratory is seeking partnerships for the following:

• Scaling Up Hardware Production: Transitioning from simulation through prototype development to demonstration of prototype capabilities for partner applications, which requires ensuring quality control and meeting industry standards.
• Software Development: Transitioning from focused proof-of-concept demonstrations through tools and diagnostics to targeted applications.