As Yogi Berra famously noted, “It’s hard to make predictions, especially about the future.” Without doubt, though, scientific discovery, business practice and social interactions are moving rapidly from a world of homogeneous and local systems to a world of distributed software, virtual organizations and cloud computing infrastructure, supported by ever larger computing infrastructure. In national defense and science, a tsunami of new experimental and computational data and a suite of increasingly ubiquitous sensors pose vexing problems in data analysis, transport, visualization and collaboration. In society and business, software as a service and cloud computing are empowering distributed groups.

Let’s step back and think about the longer term future. Where is the technology going and what are the research implications? What architectures are appropriate for 100-way or 1000-way multicore designs? How do we build scalable infrastructure? How do we develop and support software? What is the ecosystem of components in which they will operate? How do we optimize performance, power and reliability?

Biographical Sketch
Daniel A. Reed is Microsoft’s Scalable and Multicore Computing Strategist, responsible for re-envisioning the data center of the future. Previously, he was the Chancellor’s Eminent Professor at UNC Chapel Hill, as well as the Director of the Renaissance Computing Institute (RENCI) and the Chancellor’s Senior Advisor for Strategy and Innovation for UNC Chapel Hill. Dr. Reed is a member of President Bush’s Council of Advisors on Science and Technology (PCAST) and a former member of the President’s Information Technology Advisory Committee (PITAC). He recently chaired a review of the federal networking and IT research portfolio, and he is chair of the board of directors of the Computing Research Association.

He was previously Head of the Department of Computer Science at the University of Illinois at Urbana-Champaign (UIUC). He has also been Director of the National Center for Supercomputing Applications (NCSA) at UIUC, where he also led National Computational Science Alliance. He was also one of the principal investigators and chief architect for the NSF TeraGrid. He received his PhD in computer science in 1983 from Purdue University.

Presentation Slides (pdf)

MADNESS (multiresolution adaptive numerical environment for scientific simulation) is a high-level environment for performing numerical simulation with speed and precision guaranteed by use of multiresolution analysis and novel separated representations. The underlying numerical representation is discontinuous spectral element with precision maintained by dynamic adaptive refinement. The constantly changing support, the tree-like nature of the algorithms, and the goal of parallel load-balance require a similarly dynamic parallel programming model that must be compatible with our "legacy" applications. This talk will focus upon the MADNESS parallel runtime and how it facilitates a high-level composition of MADNESS itself (rather than applications upon MADNESS) as well as accommodating multi-core and hybrid architectures.

This work is funded by the U.S. Department of Energy, the divisions of Advanced Scientific Computing Research and Basic Energy Science, Office of Science, and was performed in part using resources of the National Center for Computational Sciences under contract DE-AC05-00OR22725 with Oak Ridge National Laboratory.

Presentation Slides (pdf)

With the recent achievement of petaflop/s computing and exascale computing expected in a decade, several areas of science will see dramatic changes in coming years. Future supercoputers will likely be structured differently from the past decade’s homogeneous clusters. The Roadrunner hybrid architecture, one such example, poses challenges for applications programmers who seek to migrate simulation algorithms to these platforms. Over the last two years, a number of teams have modified their applications to take advantage of the enormous increase in computational speed offered by the Cell. Some teams have achieved order-of-magnitude increases in speed over running the same applications on the Opteron chips alone. Different strategies have proved successful for the different codes. In this talk, science opportunities afforded by the dramatic increase in computing power will be outlined and application design considerations for various codes will be discussed, along with examples of different approaches taken. Science applications and modification of a specific code, the VPIC particle-in-cell plasma simulation code, will be described in more detail.

Presentation Slides (pdf)

While we are still witnessing Moore's Law by the steady production of chips that mass billions of transistors, clearly we have reached plateaus on clock frequency, power, and single stream performance. This new era has caused a rethinking of microprocessor design in search of innovations that will allow the continued performance improvement of scientific applications at an exponential rate. One technology that holds promise combines traditional microprocessors with special-purpose, very high performance, low-power chips such as the IBM Cell Broadband Engine, Graphics processors, and FPGAs, to accelerate the performance of computational science and engineering applications. The use of these chip accelerators will likely be a path forward, yet new challenges await such as system-level design, partitioning applications to accelerators, and tools for designing applications. The Sony-Toshiba-IBM Cell Broadband Engine is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE), with eight SIMD coprocessing units (SPEs) integrated on-chip. Because of the performance capabilities of the Cell BE, it is considered as an application accelerator for next-generation petascale supercomputers. Another promising technology, the Cray XMT - a massive latency-tolerent multithreaded architectures - accelerates performance on applications that use massive-scale data analytics. The XMT employs fine-grained threads to tolerate latency for irregular applications that are often challenging to parallelize on traditional cache-based architectures

Presentation Slides (pdf)

This presentation will provide a ( speculative ) 30-year outlook for semiconductor technology and microprocessor design and argue that heterogeneous multicore processors may relatively soon transition from "nice to have" to "must have". We discuss the challenges to software development and make some suggestions on how we may preserve portability of code. We will also discuss a number of Cell processor based system architectures and their relation to the various ways to program heterogeneous multicore systems in general.

While multicores built out of multiple copies of the same core appear to be homogeneous, in reality they are not. Semiconductor process variation causes different cores in the chip to have markedly different frequency and power consumption characteristics --- effectively creating a heterogenous architecture. Moreover, different cores age or wear-out differently, causing more heterogeneity. In this talk, I will describe at a high level these effects. I will also present simple architectural techniques to exploit or to minimize such heterogeneity. This includes variation-aware algorithms for power management and techniques to slow down and hide the aging of cores.

Presentation Slides (pdf)

The Roadrunner supercomputer was built by IBM for Los Alamos National Laboratory for the DOE NNSA Advanced Simulation and Computing (ASC) Program. Roadrunner was the first supercomputer to break the Petaflop/s barrier achieving 1.026 Petaflop/s on the TOP500 Linpack benchmark on May 26th, 2008. Los Alamos conceived Roadrunner as a way to enable faster, more energy-efficient and lower-cost computing through the use of acceleration devices in a hybrid computing design, in this case a modified Cell processor coupled to an AMD Opteron. Many believe that the multi-core and many-core future of micro-processors will include the use of a non-uniform mix of devices and/or cores, some of which will have special functionality. Roadrunner helps prepare for that trend.

This talk on Roadrunner will provide the configuration details of this hybrid Cell-accelerated supercomputer and how it works. It will describe the modified Cell processor, an IBM PowerXCell 8i, the hybrid TriBlade compute node developed for Roadrunner and the final system configuration. The talk will also outline programming approaches taken by early LANL applications converted to run on the accelerated Roadrunner machine; two of these applications are finalists for this year’s Gordon Bell award at SC08.

Presentation Slides (pdf)

Computer Architecture, at the processor level, will be described since the 1960’s. Then using this as a base, the fundamentals of hardware and system software design will be used to describe future processor architectures. The objective is to design the fastest heterogeneous uniprocessor that is subsequently used to scale up.

Presentation Slides (pdf)

The talk will focus on IBM's Productive Easy-to-Use Reliable Computing Systems (PERCS) funded by DARPA's HPCS. IBM's solutions to the challenges of petascale computing fall within the domains of productivity for application developers and system administrators, system efficiency, and reliability, availability, and serviceability.

Presentation Slides (pdf)

This talk will provide an overview of Cray's Cascade system, which is being developed as part of DARPA's High Productivity Computing Systems (HPCS) Program. In addition to the Cascade hardware and software architecture, features that will help achieve the productivity gains envisions by the HPCS Program will also be presented.

Presentation Slides (pdf)