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A Silicon-Based Solid State Quantum Computer
A Scaleable Architecture and the Bottom-Up Approach
The next major revolution in computing may well arise in the form of quantum computers that will far surpass conventional computers for certain specialized tasks. A quantum computer will be a computer that carries out logic operations with, and stores information in, the quantum states of a single atom, molecule, or other suitable nanoscale entity. The quantum bit, or qubit, represented by an atom or nanoengineered device is more powerful than regular bits because, due to its quantum nature, it can be put into a superposition of states. This provides a kind of massive parallelism and allows many calculations to be carried out simultaneously using only a single set of bits. This does require specialized algorithms since the final answer in the qubits cannot be "read out" in the usual sense. However, several such algorithms have already been formulated and much interest has been expressed in Shor’s factoring algorithm since a many qubit quantum computer running this algorithm could possibly decode heavily encrypted messages.
The basic ideas underlying quantum computing have already been demonstrated. Currently there are a number of several qubit devices in existence that use spins on molecules in an NMR experiment, polarization of light in lasers, or the energy levels of atoms in a Penning trap. The main problem these implementations face though is the ability to scale the number of qubits up to a useful value without succumbing to decoherence (loss of the purity of the quantum states through interaction with the local environment) or the incredible complexity involved in the apparatus that would be required to address and manipulate even 1000 qubits optically for example.
These issues led to the idea of creating a quantum computer in silicon using the spins of phosphorous atoms as the qubits as proposed by Kane in 1998 [1]. The attraction of Kane’s proposal is that it would allow the new technology to draw on the large base of existing semiconductor technology to help with qubit addressing and manipulation. In addition, it is well known that the lifetimes of dopant spin states in silicon can be very long, addressing the problem of decoherence. Our goal on this project in the SPML is to test the viability of the Kane Scheme with an operational 2-qubit device. Figure 1 shows the architecture described in Kane’s paper.
The architecture shown in Fig. 1 is based on familiar materials (phosphorus doped silicon and metal gates) and methods (NMR-based spin manipulation and electronic device type gate control). At first, fabricating such a device appeared formidable, but through our collaboration with the University of New South Wales (UNSW) in Sydney, Australia, we have been able to map out a strategy to fabricate such a structure using cutting edge technologies involving scanning tunneling microscopy (STM) and electron beam lithography. This is a bottom-up approach to the computer. UNSW is also studying a top down approach in their Centre for Quantum Computing Technology.
The bottom-up approach to realizing the Kane architecture involves making a patterned array of phosphorus nuclear spins with a 200 Å spacing on the surface of isotopically pure Si28 and then burying the array 200 Å below the surface of the silicon. Gate electrodes with lateral dimensions of less than 100 Å are then placed on the top surface to control the states of the qubits and their interactions. The gates are electrically isolated from the silicon by an insulating layer. One of the most challenging tasks for implementing Kane’s architecture appears to be producing a stable phosphorus array near, but not on the surface of a perfect silicon crystal. Ultimately, registration marks will be needed to enable electrical connections to be made to the other electronic devices.
Through our collaboration, many of these concerns have been successfully addressed by our work described below. We are now refining the initial array fabrication step and integrating the silicon overgrowth step to ensure that later processing does not destroy the array. This work is being carried out both in our scanning probe microscopy laboratory (SPML) in MST-8 and a similar facility in UNSW.
In this project, the STM is being used both as a fabrication and characterization tool in the creation of the solid state quantum computer (SSQC). STM-based atomic-scale lithography is being used to create the phosphorus arrays at room temperature in an ultra-high vacuum (UHV) variable temperature (VT) system. This atomic-scale manipulation capability is unique to the STM. In addition, the VT capability allows us to heat the sample during in-situ growth of a thin silicon overlayer by molecular beam epitaxy directly in the STM following fabrication of the patterned phosphorus array. This allows us to study the stability of the phosphorus array under pristine conditions during silicon overlayer growth and to identify potential defects and impurities that could impair the SSQC operation. Some of the steps involved in fabricating the two qubit device are described below with links to more detailed discussions.
Nanolithography
Once the clean low defect density surface is prepared, the next step in the bottom-up method is to create the phosphorus array. This will involve creating an atomic resolution pattern defining the reactive site within an un-reactive or passivated surface. These reactive sites are then exposed to phosphorus bearing molecules introduced into the vacuum chamber. Ideally the molecules bond only to the reactive sites. More.
Charge Imaging
There are a variety of issues that must be considered for successful fabrication of the SSQC. The site where the P array is created must be away from crystal dopants and defects, the array must maintain its structure during silicon overgrowth, and no new defects should appear on the surface that are detrimental to the operation of gates on the qubits. These difficulties are easily addressed by STM. All of the features of interest, i.e. buried qubits, detrimental defects, and crystal dopants, are charged at room temperature and charge can be observed with STM. The charge is what makes the defects detrimental to the SSQC, either electrically altering the extremely small gate voltages or being confused with a qubit. More.
Si Heteroepitaxy
The next step in the fabrication of the actual SSQC calls for growth of a 200 Å thick layer of crystalline silicon over the phosphorus array. The important question at this point becomes: Can crystalline silicon be grown at temperatures low enough to prevent diffusion and disruption of the array. This step can be carried out with the sample in the STM making it easier to locate the phosphorus atoms and characterize the array afterwards. Currently, we are studying epitaxial deposition of a thin silicon layer at low temperatures (<230?C) using an effusion cell small enough to be integrated into the STM chamber. More.
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Related Links
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Structure/Property Relations, MST-8