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Salishan 2005
Theme: Paths to Petaflops
Opening Address: Modeling Tsunamis with ASC Codes, Galen Gisler, LANL
Keynote Address: Petaflop-Scale
Computing (pdf), Dimitri Kusnezov, DOE, NNSA
Session 1: Exploring Requirements for Petaflops Computing
Session 2: Architecture Models for Petaflops Systems
Session 3: Other Designs for Petaflops Architectures
- FPGA-Based Petascale
Computing (pdf), Dan Poznanovic, SRC Computer, Inc.
- The CELL Processor:
Architecture and Issues (pdf), Doug Joseph, IBM
- Explicit-Communication
Architectures for Scientific Computing (pdf), William J. Dally, Stanford
University
- PIMS and CMPs for
Petaflops: how many cores can/should we place on the head of a
pin, and why? (pdf), Peter Kogge, University of Notre Dame
Session 4: System Software Tools for Petaflops Systems
Session 5: Productivity Issues for Petaflops Systems
- Colors, Conjectures, Mathematics and Productivity, Andrew B. White,
LANL
- How to Program
on 50,000 Processors (pdf), Karen Devine, SNL
- Getting Work
Out of New, High-End Systems (pdf), Mike Levine, Pittsburgh Supercomputing
Center
- HPC Productivity:
Are We Addressing the Right Issues (pdf), Cherri Pancake, Oregon
State University
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