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Los Alamos National Laboratory

Los Alamos National Laboratory

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Mitigation Working Group

Providing relevant benchmarks for testing mitigated circuits for field-programmable gate arrays and mitigated software for microprocessors.

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  • Point of Contact
  • Heather Quinn
  • Email
Mitigation Working Group

Mitigation Working Group

Benchmarking Mitigated Circuits and Software for
High-Reliability Applications

The Mitigation Working Group has been working together since January 2014 to provide relevant benchmarks for testing mitigated circuits for field-programmable gate arrays (FPGAs) and mitigated software for microprocessors. The intention of this project is to provide a standard set of codes/circuits and input vectors for testing that would cover a number of realistic compute scenarios.

The working group provides information about the unmitigated circuits/codes so there is a basis for determining whether mitigation methods effectively mask radiation- and reliability-induced errors and allows mitigation methods to be compared for power, effectiveness, and overhead.

Finally, we also provide these results with information about the compilation/synthesis process and runtime environment. We believe all of this information will provide a basis for repeatable test results and provides standards for other researchers upon which to build.

Current and Past Members
  • Miguel Aguirre, Universidad de Sevilla
  • Arno Barnard, Stellenbosch University
  • Larry Clark, Arizona State University
  • Luis Entrena, Universidad Carlos III de Madrid
  • Steven Guertin, Jet Propulsion Laboratory
  • David Kaeli, Northeastern University
  • Fernanda Lima Kastensmidt, Universidade Federal do Rio Grande do Sul
  • Heather Quinn, Los Alamos National Laboratory
  • Paolo Rech, Universidade Federal do Rio Grande do Sul
  • Matteo Sonza Reorda, Politecnico di Torino
  • William H. Robinson, Vanderbilt University
  • Luca Sterpone, Politecnico di Torino
  • Gary Swift, Swift Engineering & Radiation Services, LLC
  • Michael Wirthlin, Brigham Young University

We have telecons twice a month to discuss progress and issues with the benchmark. If you want to join the telecons, please contact Heather Quinn.

FPGA Benchmark

The FPGA benchmark leverages ITC’99. This benchmark meets all of our requirements, including a variety of realistic algorithms, defined inputs, scalability, and portability. This benchmark is specifically designed for testing and includes a set of input vectors that are designed by the automated test pattern generation community.

The working group has been actively working on testing mitigated and unmitigated versions of the B13 circuit on several FPGAs to provide a baseline for the community. In the future, we would like to test the rest of the ITC'99 circuits.

Software Benchmark

The software benchmark is more of a moving target, because there is no existing benchmark that meets our needs. We are currently using these codes in the software benchmark:

  • Advanced Encryption Standard (AES) 128,
  • Cache test,
  • CoreMark,
  • Fast Fourier Transform (FFT),
  • Hotspot,
  • HPCCG,
  • Matrix multiply (MxM), and
  • Quicksort (Qsort)

A microcontroller implementation of these codes can be found on GitHub. We've been working on standards for implementing the software codes for different classes of microprocessors, but have not completed that process yet.

Publications

H. Quinn et al., "Using Benchmarks for Radiation Testing of Microprocessors and FPGAs," in IEEE Transactions on Nuclear Science, vol. 62, no. 6, pp. 2547-2554, Dec. 2015.

H. Quinn et al., "The Use of Benchmarks for Radiation Testing”, MAPLD 2015

H. Quinn et al., "The Use of Benchmarks for High-Reliability Systems”, SELSE 2015


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